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1 tm fn9034.1 HIP6301V, hip6302v microprocessor core voltage regulator multi-phase buck pwm controller the HIP6301V and hip6302v control microprocessor core v oltage regulation by driving up to four synchronous-recti?d bu ck channels in parallel. multi-phase buck converter architecture uses interleaved timing to multiply ripple frequency and reduce input and output ripple currents. lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. the HIP6301V is a versatile two to four phase controller and the hip6302v is a cost-saving dedicated two-phase controller. the HIP6301V and hip6302v are exact pin compatible replacements for their predecessor parts, the hip6301 and hip6302. they are the ?st controllers to incorporate dynamic vid technology to manage the output voltage and current during on-the-? dac changes. using dynamic vid, the HIP6301V and hip6302v detect changes in the vid code and gradually change the reference in 25mv increments until reaching the new value. by gradually changing the reference setting, inrush current and the accompanying voltage swings remain negligibly small. intersil offers a wide range of mosfet drivers to form highly integrated solutions for high-current, high slew-rate applications. the HIP6301V and hip6302v regulate output v oltage, balance load currents and provide protective functions for two to four synchronous-recti?d buck converter channels. these parts feature an integrated high- bandwidth error ampli?r for fast, precise regulation and a ?e-bit dac for the digital interface to program the 0.8% accuracy. a window comparator toggles pgood if the output voltage moves out of range and acts to protect the load in case of over voltage. current sensing is accomplished by reading the voltage developed across the lower mosfets during their conduction intervals. current sensing provides the needed signals for precision droop, channel-current balancing, load sharing, and over-current protection. this saves cost by taking advantage of the power devices parasitic on resistance. features ? multi-phase power conversion ? precision core voltage regulation - 0.8% system accuracy over temperature ? microprocessor voltage identi cation input - dynamic-vid technology - 5-bit vid decoder ? precision channel-current balance ? overcurrent protection ? lossless current sensing ? programmable ?droop? voltage ? fast transient response ? selection of 2, 3, or 4 phase operation ? high ripple frequency (100khz to 6mhz) ordering information pinouts part number temp. ( o c) package pkg. no. HIP6301Vcb 0 to 70 20 ld soic m20.3 HIP6301Vcb-t 20 ld soic tape and reel hip6302vcb 0 to 70 16 ld soic m16.15 hip6302vcb-t 16 ld soic tape and reel 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vid4 vid3 vid2 vid1 vid0 fs/dis pwm2 pgood pwm3 isen4 isen1 v cc gnd isen3 fb pwm4 vsen comp pwm1 isen2 HIP6301V (soic) t op view 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 vid4 vid3 vid2 vid1 vid0 fs/dis vsen pgood pwm2 v cc fb comp isen2 gnd hip6302v (soic) t op view isen1 pwm1 data sheet march 2002 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ?intersil americas inc. 2002. all rights reserved dynamic vid is a trademark of intersil americas inc.
2 HIP6301V block diagram d ynamic current correction ov latch power-on reset (por) soft- start and fault logic channel detector + - uv + - e/a + - pwm pwm oc + - pwm1 pwm2 pwm3 pwm4 gnd pgood vcc fb fs/dis s three-state i_tot + + + + + - phase + - pwm + - pwm clock and number vid0 vid1 vid2 vid3 comp vsen generator sawtooth x1.15 x 0.9 isen1 isen2 isen3 isen4 vid4 vid d/a i_trip + - ov + - + - + - + - HIP6301V, hip6302v
3 hip6302v block diagram d ynamic current correction ov latch power-on reset (por) soft- start and fault logic + - uv + - e/a + - pwm pwm oc + - pwm1 pwm2 gnd pgood vcc fb fs/dis s tri-state i_tot + + + - clock and vid0 vid1 vid2 vid3 comp vsen generator sawtooth x1.15 x 0.9 isen1 isen2 vid4 vid d/a i_trip + - ov + - + - HIP6301V, hip6302v HIP6301V, hip6302v
4 HIP6301V, hip6302v HIP6301V and hip6302v functional pin descriptions vid4, vid3, vid2, vid1 and vid0 (pins 1 thru 5 - both parts) v oltage identi?ation inputs. the HIP6301V and hip6302v decode the vid bits to establish the reference voltage (see ta b le 1). each pin has an internal 20 a pull-up current source to 2.5v making the parts compatible with cmos and ttl logic from 5v down to 2.5v. when a vid change is detected the reference voltage slowly ramps up or down to the new v alue in 25mv steps. vid input levels above 2.9v may produce an reference-voltage offset inaccuracy. comp (pin 6 - both parts) output of the internal error ampli?r. connect this pin to the e xternal feedback and compensation network. fb (pin 7 - both parts) inverting input of the internal error ampli?r. fs/dis (pin 8 - both parts) channel frequency, f sw , select and disable. a resistor from this pin to ground sets the switching frequency of the converter. pulling this pin to ground disables the converter and three states the pwm outputs. see figure 10. gnd (pin 9 - both parts) bias and reference ground. all signals are referenced to this pin. vsen (pin 10 - both parts) po w er good monitor input. connect to the microprocessor- core voltage. pwm1 (pin 15 - HIP6301V, pin 14 - hip6302v), pwm2 (pin 14 -HIP6301V, pin 12 - hip6302v), pwm3 (pin 11 - HIP6301V only) and pwm4 (pin 18 - HIP6301V only) pwm outputs for each channel. connect these pins to the pwm input of the external mosfet driver. for HIP6301V systems using 3 channels, connect pwm4 high. for two channel systems, connect pwm3 and pwm4 high. isen1 (pin 16 - HIP6301V, pin 14 - hip6302v), isen2 (pin 13 - HIP6301V, pin 11 - hip6302v), isen3 (pin 12 - HIP6301V only) and isen4 (pin 17 - HIP6301V only) current sense inputs from the individual converter channels phase nodes. unused sense lines must be left open. pgood (pin 19 - HIP6301V, pin 15 - hip6302v) po w er good. this pin is an open-drain logic signal that indicates when the microprocessor core voltage (vsen pin) is within speci?d limits and soft-start has timed out. v cc (pin 20 - HIP6301V, pin 16 - hip6302v) bias supply. connect this pin to a 5v supply. 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vid4 vid3 vid2 vid1 vid0 fs/dis pwm2 pgood pwm3 isen4 isen1 v cc gnd isen3 fb pwm4 vsen comp pwm1 isen2 HIP6301V pinout 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 vid4 vid3 vid2 vid1 vid0 fs/dis vsen pgood pwm2 v cc fb comp isen2 gnd hip6302v pinout isen1 pwm1
5 t ypical application - HIP6301V controller with hip6601b gate drivers vid3 vid2 vid1 vid0 fb +5v comp pwm1 pwm2 isen2 pwm3 pwm4 isen4 vsen fs/dis isen1 isen3 gnd pgood vcc vcore main control HIP6301V vid4 pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin HIP6301V, hip6302v
6 absolute maximum ratings supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7v input, output, or i/o voltage . . . . . . . . . . gnd -0.3v to v cc + 0.3v esd classi?ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv recommended operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0? to 70? thermal information thermal resistance (typical, note 1) ja (?/w) 16 ld soic package . . . . . . . . . . . . . . . . . . . . . . . . 70 20 ld soic package . . . . . . . . . . . . . . . . . . . . . . . . 65 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150? maximum storage temperature range . . . . . . . . . . . -65? to 150? maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300? (soic - lead tips only) caution: stress above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this speci?ation is not implied. note: 1. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. (see tech brief tb379 f or details.) 2. vid input levels above 2.9v may produce an reference-voltage offset inaccuracy. electrical speci?ations operating conditions: v cc = 5v, t a = 0? to 70?, unless otherwise speci?d parameter test conditions min typ max units input supply power input supply current r t = 100k ? -1015ma en = 0v 4.25 8.8 4.5 ma por (power-on reset) threshold v cc rising 4.25 4.38 4.5 v v cc falling 3.75 3.88 4.00 v reference and dac system accuracy percent system deviation from programmed vid codes -0.8 - 0.8 % dac (vid0 - vid3) input low voltage dac programming input low threshold voltage - - 0.8 v dac (vid0 - vid3) input high voltage dac programming input high threshold voltage 2.0 - - v vid pull-up vidx = 0v or vidx = 2.5v (note 2) 10 20 40 a channel generator frequency, f sw r t = 100k ? , 1% 224 280 336 khz adjustment range see figure 10 0.05 - 1.5 mhz disable voltage maximum voltage at fs/dis to disable controller. i fs/dis = 1ma. - 1.2 1.0 v error amplifier dc gain r l = 10k to ground - 72 - db gain-bandwidth product c l = 100pf, r l = 10k to ground - 18 - mhz slew rate c l = 100pf, r l = 10k to ground - 5.3 - v/ s maximum output voltage r l = 10k to ground 3.6 4.1 - v minimum output voltage r l = 10k to ground - 0.16 0.5 v i sen full scale input current -50- a over-current trip level - 82.5 - a power good monitor under-voltage threshold vsen rising - 0.92 - v dac under-voltage threshold vsen falling - 0.90 - v dac pgood low output voltage i pgood = 4ma - 0.18 0.4 v protection overvoltage threshold vsen rising 1.12 1.15 1.2 v dac HIP6301V, hip6302v HIP6301V, hip6302v
7 operation figure 1 shows a simpli?d diagram of the voltage regulation and current control loops. both voltage and current feedback are used to precisely regulate voltage and tightly control the output currents, i l1 and i l2 , of the two power channels. the v oltage loop comprises the error ampli?r, comparators, gate drivers and output mosfets. the error ampli?r is essentially connected as a voltage follower that has as an input, the programmable reference dac and an output that is the core voltage. v oltage loop f eedback from the core voltage is applied via resistor r in to the inverting input of the error ampli?r. this signal can drive the error ampli?r output either high or low, depending upon the core voltage. low core voltage makes the ampli?r output move towards a higher output voltage level. ampli?r output voltage is applied to the positive inputs of the comparators via the correction summing networks. out- of-phase sawtooth signals are applied to the two comparators inverting inputs. increasing error ampli?r v oltage results in increased comparator output duty cycle. this increased duty cycle signal is passed through the pwm circuit with no phase reversal and on to the hip6601b, again with no phase reversal for gate drive to the upper mosfets, q1 and q3. increased duty cycle or on time for the mosfet transistors results in increased output voltage to compensate for the low output voltage sensed. current loop the current control loop works in a similar fashion to the v oltage control loop, but with current control information applied individually to each channels comparator. the percent overvoltage hysteresis vsen falling after overvoltage - 2 - % electrical speci?ations operating conditions: v cc = 5v, t a = 0? to 70?, unless otherwise speci?d parameter test conditions min typ max units current sensing comparator pwm circuit + risen1 + correction error amplifier fb reference isen1 rin vcore q3 q4 l02 phase pwm1 il2 dac cout rload vin hip6601b - q1 q2 l01 phase il1 vin hip6601b current sensing comparator pwm circuit correction pwm2 - i average + + + - programmable risen2 isen2 - - - - + + current a veraging figure 1. simplified block diagram of the HIP6301V voltage and current control loops for two-phase regulator HIP6301V, hip6302v HIP6301V, hip6302v
8 information used for this control is the voltage that is developed across r ds(on) of the lower mosfets, q2 and q4, when they are conducting. a single resistor converts and scales the voltage across the mosfets to a current that is applied to the current sensing circuit within the controller. output from these sensing circuits is applied to the current averaging circuit. each pwm channel receives the difference signal from the summing circuit that compares the average sensed current to the individual channel current. when a power channels current is greater than the average current, the signal applied via the summing correction circuit to the comparator, reduces the output pulse width of the comparator to compensate for the detected ?bove average current in that channel. droop compensation in addition to control of each power channels output current, the average channel current is also used to provide core v oltage droop compensation. average full channel current is de?ed as 50 a. by selecting an input resistor, r in , the amount of voltage droop required at full load current can be programmed. the average current driven into the fb pin results in a voltage increase across resistor r in that is in the direction to make the error ampli?r ?ee a higher voltage at the inverting input, resulting in the error ampli?r adjusting the output voltage lower. the voltage developed across r in is equal to the ?roop voltage. see the current sensing and balancing section for more details. applications and convertor start-up each pwm power channels current is regulated. this enables the pwm channels to accurately share the load current for enhanced reliability. the hip6601, hip6602 or hip6603 mosfet driver interfaces with the HIP6301V. for more information, see the datasheets for the individual intersil mosfet drivers. the HIP6301V is capable of controlling up to 4 pwm power channels. connecting unused pwm outputs to v cc automatically sets the number of channels. the phase relationship between the channels is 360 degrees/number of active pwm channels. for example, for three channel operation, the pwm outputs are separated by 120 degrees. figure 2 shows the pwm output signals for a four channel system. po w er supply ripple frequency is determined by the channel frequency, f sw , multiplied by the number of active channels. f or example, if the channel frequency is set to 250khz and there are three phases, the ripple frequency is 750khz. the ic monitors and precisely regulates the core voltage of a microprocessor. after initial start-up, the controller also provides protection for the load and the power supply. the f ollowing section discusses these features. initialization HIP6301V and hip6302v circuits usually operate from an a tx power supply. many functions are initiated by the rising supply voltage to the v cc pin of the controller. oscillator, sawtooth generator, soft-start and other functions are initialized during this interval. these circuits are controlled by por, power-on reset. during this interval, the pwm outputs are driven to a three state condition that makes these outputs essentially open. this state results in no gate drive to the output mosfets. once the v cc v oltage reaches 4.375v (?25mv), a voltage level to insure proper internal function, the pwm outputs are enabled and the soft-start sequence is initiated. if for any reason, the v cc v oltage drops below 3.875v (?25mv). the por circuit shuts the converter down and again three states the pwm outputs. soft-start after the por function is completed with v cc reaching 4.375v, the soft-start sequence is initiated. soft-start, by its slow rise in core voltage from zero, avoids an over-current condition by slowly charging the discharged output capacitors. this voltage rise is initiated by an internal dac that slowly raises the reference voltage to the error ampli?r input. the voltage rise is controlled by the oscillator frequency and the dac within the controller, therefore, the output voltage is effectively regulated as it rises to the ?al programmed core voltage value. pwm 1 pwm 2 pwm 3 pwm 4 figure 2. four phase pwm output at 500khz HIP6301V, hip6302v HIP6301V, hip6302v
9 f or the ?st 32 pwm switching cycles, the dac output remains inhibited and the pwm outputs remain three stated. f rom the 33rd cycle and for another, approximately 150 cycles the pwm output remains low, clamping the lower output mosfets to ground, see figure 3. the time variability is due to the error ampli?r, sawtooth generator and comparators moving into their active regions. after this short interval, the pwm outputs are enabled and increment the pwm pulse width from zero duty cycle to operational pulse width, thus allowing the output voltage to slowly reach the core voltage. the core voltage will reach its programmed value before the 2048 cycles, but the pgood output will not be initiated until the 2048th pwm switching cycle. the soft-start time or delay time, dt = 2048/f sw . f or an oscillator frequency, f sw , of 200khz, the ?st 32 cycles or 160 s, the pwm outputs are held in a three state level as e xplained above. after this period and a short interval described above, the pwm outputs are initiated and the voltage r ises in 10.08ms, for a total delay time dt of 10.24ms. figure 3 shows the start-up sequence as initiated by a fast r ising 5v supply, v cc, applied to the controller. note the short rise to the three state level in pwm 1 output during ?st 32 pwm cycles. figure 4 shows the waveforms when the regulator is operating at 200khz. note that the soft-start duration is a function of the channel frequency as explained previously. also note the pulses on the comp terminal. these pulses are the current correction signal feeding into the comparator input (see the block diagram on page 2). figure 5 shows the regulator operating from an atx supply. in this ?ure, note the slight rise in pgood as the 5v supply r ises.the pgood output stage is made up of nmos and pmos transistors. on the rising v cc , the pmos device becomes active slightly before the nmos transistor pulls ?own? generating the slight rise in the pgood voltage. note that figure 5 shows the 12v gate driver voltage av ailable before the 5v supply to the controller has reached its threshold level. if conditions were reversed and the 5v supply was to rise ?st, the start-up sequence would be different. in this case the controller may sense an ov ercurrent condition due to charging the output capacitors. the supply would then restart and go through the normal soft-start cycle. dynamic vid the HIP6301V and hip6302v require up to two full clock cycles to detect a change in the vid code. vid code changes that are not valid for at least two cycles may or may not be detected. once detected, the controller waits an additional two-cycle wait period to be certain the change is stable. after the two-cycle wait period, the dac begins stepping toward the new vid setting in 25mv increments. the dac makes one 25mv step every two clock cycles. for pwm 1 pgood vcore 5v output vcc vin = 12v delay time figure 3. start-up of 4 phase system operating at 500khz pgood vcore 5v v comp vcc vin = 12v delay time figure 4. start-up of 4 phase system operating at 200khz 12v atx supply pgood 5 v atx vcore supply a tx supply activated by atx ?s-on pin vin = 5v, core load current = 31a figure 5. supply powered by atx supply frequency 200khz HIP6301V, hip6302v HIP6301V, hip6302v
10 e xample, a 500khz system detecting a change from 1.300v to 1.800v requires between 84ms and 88ms to complete the change. if a new vid code is detected during a dac change and the da c can continue toward the new vid code without changing direction, processing continues without interruption. if a new vid code is detected during a dac change and the dac has to change direction in order to proceed toward then new vid code, processing halts. a two- cycle wait period is initiated and processing continues as above. these decisions are made with reference to the transitional dac value rather than the original target value. f ault protection the HIP6301V and hip6302v protect the microprocessor and the entire power system from damaging stress levels. within the controller, both overvoltage and overcurrent circuits are incorporated to protect the load and regulator. overvoltage the vsen pin is connected to the microprocessor core v oltage. a core overvoltage condition is detected when the vsen pin goes more than 15% above the programmed vid level. the overvoltage condition is latched, disabling normal pwm operation, and causing pgood to go low. the latch can only be reset by lowering and returning v cc high to initiate a por and soft-start sequence. during a latched overvoltage, the pwm outputs will be driven either low or three state, depending upon the vsen input. pwm outputs are driven low when the vsen pin detects that the core voltage is 15% above the programmed vid level. this condition drives the pwm outputs low, causing in the lower or mosfets to conduct and shunt the core voltage to ground to protect the load. if after this event, the core voltage falls below the over- v oltage limit (plus some hysteresis), the pwm outputs will three state. the hip6601 family drivers pass the three state information along, and shuts off both upper and lower mosfets. this prevents ?umping of the output capacitors back through the lower mosfets, avoiding a possibly destructive ringing of the capacitors and output inductors. if the conditions that caused the overvoltage still persist, the pwm outputs will be cycled between three state and v core clamped to ground, as a hysteretic shunt regulator. under-voltage the vsen pin also detects when the core voltage falls more than 10% below the vid programmed level. this causes pgood to go low, but has no other effect on operation and is not latched. there is also hysteresis in this detection point. over-current in the event of an over-current condition, the over-current protection circuit reduces the average current delivered to less than 25% of the current limit. when an over-current condition is detected, the controller forces all pwm outputs into a three state mode. this condition results in the gate driver removing drive to the output stages.the controller goes into a wait delay timing cycle that is equal to the soft- start ramp time. pgood also goes ?ow during this time due to vsen going below its threshold voltage.to lower the av erage output dissipation, the soft-start initial wait time is increased from 32 to 2048 cycles, then the soft-start ramp is initiated. at a pwm frequency of 200khz, for instance, an ov ercurrent detection would cause a dead time of 10.24ms, then a ramp of 10.08ms. figure 6. vcore tracking the reference voltage after a 1.85v to 1.10v change command 1.85v 5v 5v 50 s/div 1.85v pgood vref vid change vcore figure 7. vcore tracking the reference voltage after a 1.10v to 1.85v change command 1.10v 5v 5v 50 s/div 1.10v pgood vref vid change vcore HIP6301V, hip6302v HIP6301V, hip6302v
11 at the end of the delay, pwm outputs are restarted and the soft-start ramp is initiated. if a short is present at that time, the cycle is repeated. this is the hiccup mode. figure 8 shows the supply shorted under operation and the hiccup operating mode described above. note that due to the high short circuit current, overcurrent is detected before completion of the start-up sequence so the delay is not quite as long as the normal soft-start cycle. core voltage programming the voltage identi?ation pins (vid0, vid1, vid3, and vid4) set the core output voltage. each vid pin is pulled to 2.5v by an internal 20 a current source and accepts open-collector/ open-drain/open-switch-to-ground or standard low-voltage ttl or cmos signals. ta b le 1 shows the nominal dac voltage as a function of the vid codes. the power supply system is 0.8% accurate over the operating temperature and voltage range. t able 1. voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 11110 1.100 11101 1.125 11100 1.150 11011 1.175 11010 1.200 11001 1.225 11000 1.250 10111 1.275 10110 1.300 10101 1.325 pgood short 50a/div curren t a tx supply activated by atx ?s-on pin supply frequency = 200khz, v in = 12v hiccup mode. supply powered by atx supply core load current = 31a, 5v load = 5a short applied here figure 8. short applied to supply after power-up 10100 1.350 10011 1.375 10010 1.400 10001 1.425 10000 1.450 01111 1.475 01110 1.500 01101 1.525 01100 1.550 01011 1.575 01010 1.600 01001 1.625 01000 1.650 00111 1.675 00110 1.700 00101 1.725 00100 1.750 00011 1.775 00010 1.800 00001 1.825 00000 1.850 t able 1. voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vdac HIP6301V, hip6302v HIP6301V, hip6302v
12 current sensing and balancing overview the HIP6301V and hip6302v sample the on-state voltage drop across each synchronous mosfet, q2, as an indication of the inductor current in that phase, see figure 9. neglecting ac effects (to be discussed later), the voltage drop across q2 is simply r ds(on) (q2) x inductor current (i l ). note that i l , the inductor current, is either 1/2, 1/3, or 1/4 of the total current (i lt ), depending on how many phases are in use. the voltage at q2s drain, the phase node, is applied to the r isen resistor to develop the i isen current through the isen pin. this pin is held at virtual ground, so the current through r isen is . the i isen current provides information to perform the f ollowing functions: 1. detection of an overcurrent condition 2. reduce the regulator output voltage with increasing load current (droop) 3. balance the i l currents in multiple channels over-current, selecting r isen the current detected through the r isen resistor is averaged with the current(s) detected in the other 1, 2, or 3 channels. the averaged current is compared with a trimmed, internally generated current, and used to detect an overcurrent condition. the nominal current through the r isen resistor should be 50 a at full output load current, and the nominal trip point for ov ercurrent detection is 165% of that value, or 82.5 a. therefore, . f or a full load of 25a per phase, and an r ds(on) (q2) of 4m ? , r isen = 2k ? . the overcurrent trip point would be 165% of 25a, or ~ 41a per phase. the r isen value can be adjusted to change the ov ercurrent trip point, but it is suggested to stay within ?5% of nominal. droop, selection of r in the average of the currents detected through the r isen resistors is also steered to the fb pin. there is no dc return path connected to the fb pin except for r in , so the average figure 9. simplified functional block diagram showing current and voltage sampling current sensing comparator pwm circuit a veraging current from o ther channels sawtooth generator + difference risen + correction error amplifier fb comp reference to other channels isen rin rfb cc vcore q1 q2 comparator reference to o ver current trip l01 phase inductor current(s) from o ther channels pwm il dac HIP6301V cout rload vin only one output hip6601 - - stage shown - + sensing - + - + i l r ds on () q2 () r isen ------------------------------------ = r isen i l () r ds on () q2 () 50 a ---------------------------------------------- = HIP6301V, hip6302v
13 current creates a voltage drop across r in . this drop increases the apparent v core voltage with increasing load current, causing the system to decrease v core to maintain balance at the fb pin. this is the desired ?roop voltage used to maintain v core within limits under transient conditions. with a high dv/dt load transient, typical of high performance microprocessors, the largest deviations in output voltage occur at the leading and trailing edges of the load transient. in order to fully utilize the output-voltage tolerance range, the output voltage is positioned in the upper half of the range when the output is unloaded and in the lower half of the r ange when the controller is under full load. this droop compensation allows larger transient voltage deviations and thus reduces the size and cost of the output ?ter components. r in should be selected to give the desired ?roop voltage at the normal full load current 50 a applied through the r isen resistor (or at a different full load current if adjusted as under overcurrent, selecting r isen above). r in = vdroop / 50 a f or a vdroop of 80mv, r in = 1.6k ? the ac feedback components, r fb and cc, are scaled in relation to r in . current balancing the detected currents are also used to balance the phase currents. each phases current is compared to the average of all phase currents, and the difference is used to create an offset in that phases pwm comparator. the offset is in a direction to reduce the imbalance. the balancing circuit can not make up for a difference in r ds(on) between synchronous recti?rs. if a fet has a higher r ds(on) , the current through that phase will be reduced. figures 10 and 11 show the inductor current of a two phase system without and with current balancing. inductor current the inductor current in each phase of a multi-phase buck converter has two components. there is a current equal to the load current divided by the number of phases (i lt / n), and a sawtooth current, (i pk-pk ) resulting from switching. the sawtooth component is dependent on the size of the inductors, the switching frequency of each phase, and the v alues of the input and output voltage. ignoring secondary effects, such as series resistance, the peak to peak value of the sawtooth current can be described by: where: v core = dc value of the output or v id voltage v in = dc value of the input or supply voltage l= value of the inductor f sw = switching frequency example: for v core = 1.6v, v in = 12v, l= 1.3 h, f sw = 250khz, then i pk-pk = 4.3a the inductor, or load current, ?ws alternately from v in through q1 and from ground through q2. the controller samples the on-state voltage drop across each q2 transistor to indicate the inductor current in that phase. the voltage drop is sampled 1/3 of a switching period, 1/f sw , after q1 is turned off and q2 is turned on. because of the sawtooth current component, the sampled current is different from the av erage current per phase. neglecting secondary effects, i pk pk v in v core () v 2 core l () f sw () v in () ----------------------------------------------------------------- = 0 5 10 15 20 25 amperes figure 10. two channel multiphase system with current balancing disabled 0 5 10 15 20 25 amperes figure 11. two channel multiphase system with current balancing enabled HIP6301V, hip6302v HIP6301V, hip6302v
14 the sampled current (i sample ) can be related to the load current (i lt ) by: where: i lt = total load current n= the number of channels example: using the previously given conditions, and for i lt = 100a, n= 4 then i sample = 25.49a as discussed previously, the voltage drop across each q2 transistor at the point in time when current is sampled is r dson (q2) x i sample . the voltage at q2s drain, the phase node, is applied through the r isen resistor to the HIP6301V isen pin. this pin is held at virtual ground, so the current into isen is: example: from the previous conditions, where i lt = 100a, i sample = 25.49a, r ds(on) (q2) = 4m ? then: r isen = 2.04k and i current trip = 165% short circuit i lt = 165a. channel frequency oscillator the channel oscillator frequency is set by placing a resistor, r t , to ground from the fs/dis pin. figure 12 is a curve showing the relationship between frequency, f sw, and resistor r t . to av oid pickup by the fs/dis pin, it is important to place this resistor next to the pin. layout considerations mosfets switch very fast and ef?iently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade ef?iency, radiate noise into the circuit and lead to device overvoltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel current. during the turnoff, current stops ?wing in the upper mosfet and is picked up by the lower mosfet. any inductance in the s witched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. contact intersil for evaluation board drawings of the component placement and printed circuit board. there are two sets of critical components in a dc-dc converter using a HIP6301V or hip6302v controller and a hip6601 family gate driver. the power components are the most critical because they switch large amounts of energy. next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. the power components should be placed ?st. locate the input capacitors close to the power switches. minimize the length of the connections between the input capacitors, c in , and the power switches. locate the output inductors and output capacitors between the mosfets and the load. locate the gate driver close to the mosfets. the critical small components include the bypass capacitors f or vcc and pvcc on the gate driver ics. locate the bypass capacitor, c bp , for the controller close to the device. it is especially important to locate the resistors associated with the input to the ampli?rs close to their respective pins, since they represent the input to feedback ampli?rs. resistor r t , that sets the oscillator frequency should also be located next to the associated pin. it is especially important to place the r sen resistor(s) at the respective isen terminals. a multi-layer printed circuit board is recommended. figure 13 shows the connections of the critical components for one output channel of the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually the middle layer of the pc board, for a g round plane and make all critical component ground i sample i lt n ------- - v in () v core 3v 2 core + 6l () f sw () v in () ----------------------------------------------------------------------------------- - = i sense i sample () r ds on () q2 () r isen ------------------------------------------------------------------ - = r isen i sample () r ds on () q2 () 50 a ------------------------------------------------------------------ - = 50 100 10 20 200 500 1,000 5,000 10,000 2,000 1 2 5 10 20 50 100 200 500 1,000 rt (kw) channel oscillator frequency, fsw (khz) figure 12. resistance r t vs frequency HIP6301V, hip6302v HIP6301V, hip6302v
15 connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to inductor l o1 short. the power plane should support the input power and output power nodes. use copper ?led polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the driver ic to the mosfet gate and source should be sized to carry at least one ampere of current. component selection guidelines output capacitor selection the output capacitor is selected to meet both the dynamic load requirements and the voltage ripple requirements. the load transient for the microprocessor core is characterized by high slew rate (di/dt) current demands. in general, m ultiple high quality capacitors of different size and dielectric are paralleled to meet the design constraints. modern microprocessors produce severe transient load rates. high frequency capacitors supply the initially transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk ?ter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on speci? decoupling requirements. use only specialized low-esr capacitors intended for s witching-regulator applications for the bulk capacitors. the b ulk capacitors esr determines the output ripple voltage and the initial voltage drop following a high slew-rate transients edge. in most cases, multiple capacitors of small case size perform better than a single large case capacitor. bulk capacitor choices include aluminum electrolytic, os- con, tantalum and even ceramic dielectrics. an aluminum electrolytic capacitors esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a speci?d parameter. consult the capacitor manufacturer and measure the capacitors impedance with frequency to select a suitable component. output inductor selection one of the parameters limiting the converters response to a load transient is the time required to change the inductor current. small inductors in a multi-phase converter reduces the response time without signi?ant increases in total ripple current. the output inductor of each power channel controls the r ipple current. the control ic is stable for channel ripple current (peak-to-peak) up to twice the average current. a single channels ripple current is approximately: the current from multiple channels tend to cancel each other and reduce the total ripple current. figure 14 gives the total r ipple current as a function of duty cycle, normalized to the parameter at zero duty cycle. to determine the total ripple current from the number of channels and the duty cycle, multiply the y-axis value by . ? i v in v out f sw l ------------------------------- - v out v in --------------- - = vcore +12v via connection to ground plane island on power plane layer island on circuit plane layer lo1 cout cin +5vin key phase vcc use individual metal runs comp HIP6301V pwm r t r in r fb c bp fb vsen isen r sen hip6601 cboot cbp c t v cc fs/dis pvcc locate next to ic pin locate next to fb pin locate next to ic pin(s) isolate output stages for each channel to help locate near transistor figure 13. printed circuit board power planes and islands vo () lxf sw () vo () lxf sw () HIP6301V, hip6302v
16 small values of output inductance can cause excessive power dissipation. the HIP6301V and hip6302v are designed for stable operation for ripple currents up to twice the load current. however, for this condition, the rms current is 115% above the value shown in the following mosfet selection and considerations section. with all else ?ed, decreasing the inductance could increase the power dissipated in the mosfets by 30%. input capacitor selection the important parameters for the bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor v oltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current required for a m ulti-phase converter can be approximated with the aid of figure 15. first determine the operating duty ratio as the ratio of the output voltage divided by the input voltage. find the current m ultiplier from the curve with the appropriate power channels. multiply the current multiplier by the full load output current. the resulting value is the rms current rating required by the input capacitor. use a mix of input bypass capacitors to control the voltage ov ershoot across the mosfets. use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors should be placed ve ry close to the drain of the upper mosfet to suppress the v oltage induced in the parasitic circuit impedances. f or bulk capacitance, several electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv-gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution m ust be exercised with regard to the capacitor surge current r ating. these capacitors must be capable of handling the surge-current at power-up. the tps series available from a vx, and the 593d series from sprague are both surge current tested. 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) ripple current (a peak-peak ) v o / (l x f sw ) single channel 2 channel 3 channel 4 channel figure 14. ripple current vs duty cycle 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) current multiplier single channel 3 channel 4 channel 2 channel figure 15. current multiplier vs duty cycle HIP6301V, hip6302v
17 mosfet selection and considerations in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty factor (see the following equations). the conduction losses are the main component of power dissipation for the lower mosfets, q2 and q4 of figure 1. only the upper mosfets, q1 and q3 have signi?ant switching losses, since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfets body diode. the gate-charge losses are dissipated by the driver ic and don't heat the mosfets. however, large gate-charge increases the switching time, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance speci?ations. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air ?w. a diode, anode to ground, may be placed across q2 and q4 of figure 1. these diodes function as a clamp that catches the negative inductor swing during the dead time between the turn off of the lower mosfets and the turn on of the upper mosfets. the diodes must be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. it is usually acceptable to omit the diodes and let the body diodes of the lower mosfets clamp the negative inductor swing, but ef?iency could drop one or two percent as a result. the diode's rated reverse breakdown voltage m ust be greater than the maximum input voltage. p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f sw 2 --------------------------------------------------------- - + = p lower i o 2 r ds on () v in v out () v in -------------------------------------------------------------------------------- - =
18 HIP6301V, hip6302v small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list?in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ??does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93
19 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporations quality certi?ations can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft w are and/or speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. f or information regarding intersil corporation and its products, see www.intersil.com sales of?e headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 HIP6301V, hip6302v small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list?in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ??does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 o 8 o 0 o 8 o - rev. 0 12/93

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